Publications

Conference

• [C3] HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
  Y. Zhang, C. Ma, J. Ge, L. Jiang, J. Xu, W. Zhang
  IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2026 [Accepted]
  

• [C2] FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
  X. Liu, J. Liang, L. Du, Y. Zhang, C. Ma, H. Fan, J. Xu, W. Zhang
  International Conference on Parallel Processing (ICPP), 2025
  

• [C1] SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices [PDF]
  Y. Zhang, J. Liang, J. Peng, J. Xu, W. Zhang
  Design, Automation & Test in Europe Conference & Exhibition (DATE), 2025

Journal

• [J1] Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator
  J. Peng, T. Liang, J. Jiang, Y. Zhang, Z. Lin, Z. Xie, W. Zhang
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’24)